With the rapid expansion of social media and online communication platforms, the proliferation of toxic comments such as hate speech, harassment, and offensive language—has become a significant concern. Detecting and moderating such content is crucial for maintaining healthy digital interactions. This paper presents an overview of machine learning (ML) methods used for online toxic comment classification. Various supervised and deep learning approaches, including Logistic Regression, Support Vector Machines (SVM), Random Forests, Recurrent Neural Networks (RNN), and Convolutional Neural Networks (CNN), are analyzed for their performance in identifying toxic behavior in textual data. The study emphasizes the importance of data preprocessing, feature extraction techniques (such as TF-IDF and word embeddings), and model optimization for improving classification accuracy. It also highlights recent advancements in transformer-based models like BERT, which achieve superior context understanding and robustness. Challenges such as data imbalance, context ambiguity, and evolving language patterns are discussed. The paper concludes that integrating traditional ML with deep learning and Natural Language Processing (NLP) techniques offers a powerful solution for effective and scalable toxic comment detection.

Keywords : Machine learning, Toxic comment classification, NLP, Deep learning, Online moderation

Authors : Kondala Geethanjali

Title : Machine Learning methods for Online Toxic Comment Classification

Volume/Issue : 2021;3(5 (September - October))

Page No : 5 - 9

The increasing demand for high-speed and energy-efficient Digital Signal Processing (DSP) systems has led to the development of optimized Very Large Scale Integration (VLSI) architectures. This paper presents the design and simulation of a 32-bit Parallel Self-Timed Adder (PASTA) architecture tailored for DSP processors. The PASTA architecture employs asynchronous logic design principles to achieve faster computation with reduced power consumption and delay compared to conventional ripple-carry or carry-lookahead adders. The proposed 32-bit VLSI design is modeled using hardware description languages (HDL) and simulated on standard EDA tools to evaluate performance parameters such as propagation delay, area utilization, and power efficiency. Simulation results demonstrate that the 32-bit PASTA architecture significantly enhances arithmetic performance, making it suitable for high-speed DSP applications including filtering, convolution, and real-time signal analysis. The study concludes that PASTA-based architectures provide an effective solution for achieving optimized speed-power trade-offs in next-generation DSP processor designs.

Keywords : VLSI design, PASTA, DSP processors, Asynchronous circuits, High-speed adders

Authors : K.Kanaka Kumari

Title : Design and Simulation of VLSI architecture of a 32 Bit PASTA for DSP Processors

Volume/Issue : 2021;3(5 (September - October))

Page No : 1 - 4